module cache_tag_ram (
    input clk,
    input rst,
    input [9:0] idex,
    input we,
    input write_cache_line_vbit,
    input write_cache_line_dbit,
    input [17:0]write_cache_line_tagf,
    output cache_line_vbit,
    output cache_line_dbit,
    output [17:0]cache_line_tagf
);
//bit field:
//bit 19: valid bit
//bit 18: dirty bit
//bit 17~0 : tag

reg [19:0] tag_mem[0:1023];

integer i;

//read
assign {cache_line_vbit,cache_line_dbit,cache_line_tagf} = tag_mem[idex];

//write
always @(posedge clk) begin
    if(rst) begin
        for(i=0;i<1024;i=i+1)
            tag_mem[i] <= 'd0;
    end
    else begin
        if(we) begin
            tag_mem[idex] <= {write_cache_line_vbit,write_cache_line_dbit,write_cache_line_tagf};
        end
    end
end

endmodule //cache_tag_ram